1. Field of the Invention
The present invention relates to a synchronous rectifier, in particular, but not exclusively, for use in mobile applications.
2. Discussion of the Related Art
As known, mobile applications require high-efficiency synchronous rectifiers, having precise on/off switching times, where a diode that dissipates most of the power. Such applications include particularly Switched Mode Power Supplies (SMPS) of all topologies. In the following, reference will be made to a step down (buck) converter, although the invention is not limited thereto, but can be used in any application where rectification efficiency is needed.
A typical buck converter 1 is shown in FIG. 1. The buck converter 1 comprises an inductor L storing energy from a power supply VCC (for example a battery) and transferring the stored energy to an output node OUT; a switch T1, here a PMOS transistor, for connecting the power supply VCC to a first terminal of the inductor L (node LX between the inductor L and the switch T1) during a charging step and disconnecting the inductor L from the power supply VCC during an energy transfer step; a freewheeling diode D, connecting the first terminal of the inductor L to ground and allowing recirculation of the inductor current IL during the energy transfer step; an output capacitor CO connected to the output node OUT (second terminal of the inductor L) for filtering an output voltage VO; a second switch T2, here an NMOS transistor, connected in parallel to the diode D; a feedback circuit including an integrator (error amplifier) EA and a first comparator Comp1, connected to the output node OUT; and a logic circuit 5 receiving an output signal of the feedback circuit, Comp1 and generating a first and a second control signals s1, s2 for, respectively, the first and second switches T1, T2. In a known manner, integrator EA receives the output voltage VO and a reference voltage VREF and generates an error signal e fed to the first comparator Comp1; first comparator Comp1 also receives a saw-tooth signal and generates a duty-cycle signal s3 used by logic circuit 5 to drive switches T1 and T2.
In the simplest implementation, NMOS transistor T2 is not necessary and the conduction of the recirculation current is carried out by diode D. The disadvantage in using only diode D resides in the large power loss when diode D is forward biased (i.e., during the freewheeling period). In particular, the power losses P are approximately given by:
  P  =            1      T        ⁢                  ∫                  t          1                          t          2                    ⁢                        V          FD                ⁢                  I          L                ⁢                                  ⁢                  ⅆ          t                    
wherein:
1/T is the working frequency of the converter 1;
t2−t1 is the conduction time of the diode D;
IL is the current through the inductor L (equal to the diode current in the recirculation step);
and VFD is the diode forward voltage.
Since Schottky diodes have a lower forward voltage as compared to PN diodes, they are preferred and allow an improvement of the recirculation losses by a factor of two.
A further improvement is obtained through NMOS transistor T2, which can be driven so as to have a very low voltage drop. NMOS transistor T2 is controlled by control signal s2 so as to be on only during the recirculation step, as explained in greater detail hereinafter, with reference to the plots of FIG. 2. FIG. 2 show the behavior of the current IL flowing through the inductor L and of the voltage VLX on node LX in case of a small load connected to the output OUT of the converter 1.
Initially, at time t0, PMOS transistor T1 is switched on and connects node LX to the power supply Vcc; NMOS transistor T2 is off. Thus the inductor current IL rises linearly with a slope SL:SL=(Vcc−VO)/L 
wherein L is the inductance of the inductor L.
At time t1, determined by the feedback circuit EA, Comp1, PMOS transistor T1 is switched off and NMOS transistor T2 is switched on. Thereafter, neglecting the negative spike due to the switching-on time of the NMOS transistor T2, voltage VLX is equal to the voltage drop across NMOS transistor T2 and depends on the resistance RDSon of the NMOS transistor T2 and the recirculation current IL, as follows:VLX=−(RDson*IL).  (1)
When inductor current IL reaches zero (time t2), neglecting a negative spike due to the switching-off time of the NMOS transistor T2, voltage VLX becomes equal to the output voltage VO, in turn equal to the reference voltage VREF.
In this circuit, the correct timing of both turning-on and turning-off of the NMOS transistor T2 is critical. In fact:                if NMOS transistor T2 is turned on too early, some charging current flows from the power supply to ground, causing undesired power consumption and reduction in efficiency;        if NMOS transistor T2 is turned on too late or is turned off too early, part of the recirculation current flows through the diode D, causing large losses on the same;        if NMOS transistor T2 is turned off too late, the inductor current IL reverses and reduces the overall efficiency.        
There are very different design requirements for the logic circuit 5 managing the turn on and turn off control signals s1, s2. For example, the design requirements are dictated by the operation mode, i.e., whether the step-down converter 1 is operated in Pulse Width Modulation PWM mode or in Pulse Frequency Modulation PFM mode. In fact, the PFM mode is totally asynchronous, thus preventing the use of any solution based on periodic clocking.
However, ideally, the design should cover both operation modes, that is any type of Discontinuous Conduction Mode DCM.
Hereinafter, in particular the problem of exactly determining the switching-off instant of the NMOS transistor T2 will be addressed.
As indicated, the NMOS transistor T2 should be ideally switched off when the current IL through the inductor L exactly reaches the zero value. According to a possible solution, shown in FIG. 3, the current IL through the inductor L is sensed by a sense resistor Rs arranged in series to the NMOS transistor T2 and diode D. The voltage across the sense resistor Rs is detected by a second comparator Comp2 which generates a suitable signal Z when current IL reaches zero. Signal Z is fed to the logic circuit 5 to cause switching off of the NMOS transistor T2.
In this solution, the resistance of the sense resistor Rs should satisfy conflicting requirements. In fact, the larger the resistance, the higher the current-to-voltage gain and thus the accuracy of the second comparator Comp2. However, the larger the resistance, the larger the losses on the sense resistor Rs. Thus such a solution is not suitable for high efficiency applications.
According to a different solution, the resistive behavior of the NMOS transistor T2 is exploited, as shown in FIG. 4. In fact, according to (1), during the energy transfer step, NMOS transistor T2 has a voltage drop proportional to its RDSon, which can be used for detecting the inductor current. In this case, a zero comparator ZComp has a first input connected to node LX, a second input connected to ground, and an output supplying a zero signal ZC and connected to the logic circuit 5.
RDSon has a very low value (of about 100 mΩ), which puts extreme requirements on the zero comparator ZComp in terms of input offset and propagation delay.
In fact, the attainable input offset is greater than the quantity to be measured. This is clear from consideration of the plots FIGS. 5a and 5b. FIG. 5a shows an enlarged portion of the current IL and the voltage VLX near time t2 (neglecting the voltage spike). FIG. 5b shows a typical distribution of the comparator offset of a CMOS process usable for the intended application. In particular, for an inductor current IL=10 mA, assuming RDSon=100 mΩ, VLX=1 mV. Typical matching characteristics of a CMOS process give an offset comprised in a ±8 mV range. Therefore the zero comparator ZComp should measure a 1 mV voltage with a ±8 mV accuracy. This is not possible, since a 8 mV offset may cause the zero comparator ZComp to generate the zero signal ZC and thus switching off of the NMOS transistor T2 while 80 mA are still flowing through the inductor L. Considering that the peak value of the inductor current IL may be comprised between 100 and 150 mA, the synchronous rectifier would be inefficient for most of the time.
A source of error also lies in the propagation time, that is the time needed by the zero comparator ZComp to generate the zero signal ZC after detecting the zero condition (also called decision time). As known, the propagation time also depends on the voltage level at the input of the zero comparator ZComp. A low voltage level causes the decision time of the zero comparator ZComp to dramatically extend. For example, a zero comparator driven with a 1V/μs triangular waveform may have a decision time of 8 ns, while the same comparator drive with a 1 μV/μs has a 45 ns decision time. Since the inductor current slope SIL for an output voltage VO=2V and an inductance L=4.7 μH is:SIL=(VLX−VO)/L≈−2 V/4.7 μH≈−0.4 A/μsthe propagation delay may cause the NMOS transistor T2 to switch off when the inductor current reaches −0.4 A/μs*45 ns=−18 mA. Such a reverse current in the inductor L is not acceptable.